View MAX19708ETM-T_6129234.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max19708 is an ultra-low-power, mixed-signal ana- log front-end (afe) designed for td-scdma handsets and data cards. optimized for high dynamic perfor- mance at ultra-low power, the device integrates a dual 10-bit, 11msps receive (rx) adc; dual 10-bit, 11msps transmit (tx) dac with td-scdma baseband filters; three fast-settling 12-bit aux-dac channels for ancillary rf front-end control; and a 10-bit, 333ksps housekeep- ing aux-adc. the typical operating power in tx-rx fast mode is 36.9mw at a 5.12mhz clock frequency. the rx adcs feature 55db snr and 77.4 dbc sfdr at a 1.87mhz input frequency with an 11mhz clock frequen- cy. the analog i/q input amplifiers are fully differential and accept 1.024v p-p full-scale signals. typical i/q channel matching is 0.08 phase and 0.02db gain. the tx dacs with td-scdma lowpass filters feature -3db cutoff frequency of 1.32mhz and > 55db stopband rejec- tion at f image = 4.32mhz. the analog i-q full-scale output voltage range is selectable at ?10mv or ?00mv differ- ential. the output dc common-mode voltage is selec- table from 0.9v to 1.4v. the i/q channel offset is adjustable to optimize radio lineup sideband/carrier sup- pression. typical i-q channel matching is 0.02db gain and 0.04 phase. the rx adc and tx dac share a single, 10-bit parallel, high-speed digital bus allowing half-duplex operation for time-division duplex (tdd) applications. a 3-wire serial interface controls power-management modes, the aux-dac channels, and the aux-adc channels. the max19708 operates on a single +2.7v to +3.3v analog supply and +1.8v to +3.3v digital i/o supply. the max19708 is specified for the extended (-40? to +85?) temperature range and is available in a 48-pin, thin qfn package. the selector guide at the end of the data sheet lists other pin-compatible versions in this afe family. applications td-scdma handsets td-scdma data cards portable communication equipment features ? dual 10-bit, 11msps rx adc and dual 10-bit, 11msps tx dac ? ultra-low power 36.9mw at f clk = 5.12mhz, fast mode 19.8mw at f clk = 5.12mhz, slow mode low-current standby and shutdown modes ? integrated td-scdma filters with > 55db stopband rejection ? programmable tx dac common-mode dc level and i/q offset trim ? excellent dynamic performance snr = 55db at f in = 1.87mhz (rx adc) sfdr = 73dbc at f out = 620khz (tx dac) ? three 12-bit, 1? aux-dacs ? 10-bit, 333ksps aux-adc with 4:1 input mux and data averaging ? excellent gain/phase match ?.08 phase, ?.02db gain (rx adc) at f in = 1.87mhz ? multiplexed parallel digital i/o ? serial-interface control ? versatile power-control circuits shutdown, standby, idle, tx/rx disable ? miniature 48-pin thin qfn package (7mm x 7mm x 0.8mm) max19708 10-bit, 11msps, ultra-low-power analog front-end ________________________________________________________________ maxim integrated products 1 19-3764; rev 0; 8/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information part* pin-package pkg code max19708etm 48 thin qfn-ep** t4877-4 max19708etm+ 48 thin qfn-ep** t4877-4 * all devices are specified over the -40c to +85? operating range. ** ep = exposed paddle. + denotes lead-free package. functional diagram and selector guide appear at end of data sheet. d9 d8 d6 ov dd d4 d3 d2 d0 d1 ognd d5 d7 v dd idn idp gnd v dd qdn qdp refn exposed paddle (gnd) refin dac1 com dac2 37 38 39 40 41 42 43 44 45 46 47 48 1234 5 67 89 10 24 23 22 21 20 19 18 17 16 15 14 13 adc1 adc2 v dd gnd v dd cs sclk din t/r shdn dout dac3 thin qfn max19708 top view refp v dd iap ian gnd clk gnd v dd qan qap v dd gnd 11 12 36 35 34 33 32 31 30 29 28 27 26 25 pin configuration
max19708 10-bit, 11msps, ultra-low-power analog front-end 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd, ov dd to ognd ..............................-0.3v to +3.6v gnd to ognd.......................................................-0.3v to +0.3v iap, ian, qap, qan, idp, idn, qdp, qdn, dac1, dac2, dac3 to gnd .....................-0.3v to v dd adc1, adc2 to gnd.................................-0.3v to (v dd + 0.3v) refp, refn, refin, com to gnd ...........-0.3v to (v dd + 0.3v) d0?9, dout, t/ r , shdn , sclk, din, cs , clk to ognd .....................................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70?) 48-pin thin qfn (derate 27.8mw/? above +70?) .....2.22w thermal resistance ja ..................................................36?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 11mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units power requirements analog supply voltage v dd 2.7 3.0 3.3 v output supply voltage ov dd 1.8 v dd v ext1-tx, ext3-tx, and spi2-tx states; transmit dac operating mode (tx): f clk = 5.12mhz, f out = 620khz on both channels; aux-dacs on and at midscale, aux-adc on 10.3 ext2-tx, ext4-tx, and spi4-tx states; transmit dac operating mode (tx): f clk = 5.12mhz, f out = 620khz on both channels; aux-dacs on and at midscale, aux-adc on 12.6 ext1-rx, ext4-rx, and spi3-rx states; receive adc operating mode (rx): f clk = 5.12mhz, f in = 1.87mhz on both channels; aux-dacs on and at midscale, aux-adc on 12.3 ext2-rx, ext3-rx, and spi1-rx states; receive adc operating mode (rx): f clk = 5.12mhz, f in = 1.87mhz on both channels; aux-dacs on and at midscale, aux-adc on 6.6 v dd supply current ext2-tx, ext4-tx, and spi4-tx states; transmit dac operating mode (tx): f clk = 11mhz, f out = 620khz on both channels, aux-dacs on and at midscale, aux-adc on 14.1 16 ma
max19708 10-bit, 11msps, ultra-low-power analog front-end _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 11mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units ext1-tx, ext3-tx, and spi2-tx states; transmit dac operating mode (tx): f clk = 11mhz, f out = 620khz on both channels, aux-dacs on and at midscale, aux-adc on 11.7 ext1-rx, ext4-rx, and spi3-rx states; receive adc operating mode (rx): f clk = 11mhz, f in = 1.87mhz on both channels, aux-dacs on and at midscale, aux-adc on 13.7 16 ext2-rx, ext3-rx, and spi1-rx states; receive adc operating mode (rx): f clk = 11mhz, f in = 1.87mhz on both channels, aux-dacs on and at midscale, aux-adc on 8 standby mode: clk = 0 or ov dd ; aux-dacs on and at midscale, aux-adc on 2.9 4 idle mode: f clk = 11mhz; aux-dacs on and at midscale, aux-adc on 5.5 7 ma v dd supply current shutdown mode: clk = 0 or ov dd 0.52 ? ext1-rx, ext2-rx, ext3-rx, ext4-rx, spi1-rx, spi3-rx states; receive adc operating mode (rx): f clk = 11mhz, f in = 1.87mhz on both channels; aux-dacs on and at midscale, aux-adc on 1.5 ma ext1-tx, ext2-tx, ext3-tx, ext4-tx, spi2-tx, spi4-tx states; transmit dac operating mode (tx): f clk = 11mhz, f out = 620khz on both channels; aux-dacs on and at midscale, aux-adc on 110 standby mode: clk = 0 or ov dd ; aux- dacs on and at midscale, aux-adc on 1 idle mode: f clk = 11mhz; aux-dacs on and at midscale, aux-adc on 19 ov dd supply current shutdown mode: clk = 0 or ov dd 0.1 ?
max19708 10-bit, 11msps, ultra-low-power analog front-end 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 11mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units rx adc dc accuracy resolution n 10 bits integral nonlinearity inl ?.9 lsb differential nonlinearity dnl guar anteed no m i ssi ng cod e ( n ote 2) -1.0 ?.4 +1.2 lsb offset error residual dc offset error -5 ?.1 +5 %fs gain error include reference error -7.0 ?.5 +10.5 %fs dc gain matching -0.25 ?.01 +0.25 db offset matching ?0 lsb gain temperature coefficient ?8.4 ppm/? offset error (v dd ?%) ? lsb power-supply rejection psrr gain error (v dd ?%) ?.07 %fs rx adc analog input input differential range v id differential or single-ended inputs ?.512 v input common-mode voltage range v cm v dd / 2 v r in switched capacitor load 491 k input impedance c in 5pf rx adc conversion rate maximum clock frequency f clk (note 3) 11 mhz channel i 5 data latency (figure 3) channel q 5.5 clock cycles rx adc dynamic characteristics (note 4) f in = 1.875mhz, f clk = 11mhz 53.3 55 signal-to-noise ratio snr f in = 3.5mhz, f clk = 11mhz 55 db f in = 1.875mhz, f clk = 11mhz 53.2 54.9 signal-to-noise and distortion sinad f in = 3.5mhz, f clk = 11mhz 54.9 db f in = 1.875mhz, f clk = 11mhz 63.5 77.4 spurious-free dynamic range sfdr f in = 3.5mhz, f clk = 11mhz 78.3 dbc f in = 1.875mhz, f clk = 11mhz -84.3 third-harmonic distortion hd3 f in = 3.5mhz, f clk = 11mhz -85 dbc intermodulation distortion imd f 1 = 1.8mhz, -7dbfs; f 2 = 1mhz, -7dbfs -72.7 dbc third-order intermodulation distortion im3 f 1 = 1.8mhz, -7dbfs; f 2 = 1mhz, -7dbfs -74.4 dbc f in = 1.875mhz, f clk = 11mhz -75.6 -63 total harmonic distortion thd f in = 3.5mhz, f clk = 11mhz -76.3 db aperture delay 3.5 ns overdrive recovery time 1.5x full-scale input 2 ns
max19708 10-bit, 11msps, ultra-low-power analog front-end _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 11mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units rx adc interchannel characteristics crosstalk rejection f in x ,y = 1.875m h z at - 0.5d bfs , f in x ,y = 1m h z at - 0.5d bfs ( n ote 5) -90 db amplitude matching f in = 1.875mhz at -0.5dbfs (note 6) ?.02 db phase matching f in = 1.875mhz at -0.5dbfs (note 6) ?.08 d eg r ees tx dac dc accuracy resolution n 10 bits integral nonlinearity inl ?.45 lsb differential nonlinearity dnl guaranteed monotonic (note 2) -1 ?.4 +1 lsb t a > +25? -4 ? +4 residual dc offset v os t a < +25? -5.5 ? +5.5 mv full-scale gain error incl ud e r efer ence er r or ( p eak- to- p eak er r or ) -50 +50 mv tx path dynamic performance corner frequency 3db corner 1.05 1.32 1.65 mhz passband ripple dc to 640khz (note 2) 0.15 0.5 db p-p group delay variation in passband dc to 640khz 50 ns error-vector magnitude evm dc to 700khz 2 % stopband rejection f image = 4.32mhz, f out = 800khz, f clk = 5.12mhz 55 62.5 dbc 2mhz 21.5 4mhz 49 5mhz 58 10mhz 90 baseband attenuation spot relative to 100khz 20mhz 90 db dac conversion rate f clk (note 3) 11 mhz in-band noise density n d f out = 620khz, f clk = 5.12mhz, offset = 500khz -120.6 dbc/hz third-order intermodulation distortion im3 f 1 = 620khz, f 2 = 640khz 82 dbc glitch impulse 10 pv s spurious-free dynamic range to nyquist sfdr f clk = 11mhz, f out = 620khz 60 73 dbc total harmonic distortion to nyquist thd f clk = 11mhz, f out = 620khz -71 -60 db signal-to-noise ratio to nyquist snr f clk = 11mhz, f out = 620khz 56.5 db
max19708 10-bit, 11msps, ultra-low-power analog front-end 6 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 11mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units tx path interchannel characteristics i-to-q output isolation f outx,y = 500khz, f outx,y = 620khz 90 db gain mismatch between dac outputs measured at dc -0.30 ?.02 +0.31 db phase mismatch between dac outputs f out = 620khz, f clk = 11mhz ?.04 d eg r ees differential output impedance 800 tx path analog output bit e7 = 0 (default) ?10 full-scale output voltage (table 8) v fs bit e7 = 1 ?00 mv bits cm1 = 0, cm0 = 0 (default) 1.27 1.4 1.48 bits cm1 = 0, cm0 = 1 1.25 bits cm1 = 1, cm0 = 0 1.1 output common-mode voltage (table 11) v com bits cm1 = 1, cm0 = 1 0.9 v rx adc?x dac interchannel characteristics receive transmit isolation adc f ini = f inq = 1.875mhz, dac f outi = f outq = 620khz, f clk = 11mhz 90 db auxiliary adc (adc1, adc2) resolution n 10 bits ad1 = 0 (default) 2.048 full-scale reference v ref ad1 = 1 v dd v analog input range 0 to v ref v analog input impedance at dc 500 k input-leakage current measured at unselected input from 0 to v ref ?.1 ? gain error ge includes reference error -5 +5 %fs zero-code error ze 2 mv differential nonlinearity dnl ?.53 lsb integral nonlinearity inl ?.45 lsb supply current 210 ?
max19708 10-bit, 11msps, ultra-low-power analog front-end _______________________________________________________________________________________ 7 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 11mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units auxiliary dacs (dac1, dac2, dac3) resolution n 12 bits integral nonlinearity inl ?.25 lsb differential nonlinearity dnl guaranteed monotonic over codes 100 to 4000 (note 2) -1.0 ?.65 +1.2 lsb gain error ge r l > 200k 0.1 v output-voltage high v oh r l > 200k settling time from 1/4 fs to 3/4 fs, within ?0 lsb 1 s glitch impulse from 0 to fs transition 24 nv s rx adc-tx dac timing characteristics clk rise to channel-i output data valid t doi figure 3 (note 2) 5.3 7.0 8.5 ns clk fall to channel-q output data valid t doq figure 3 (note 2) 6.8 9.1 11.3 ns i-dac data to clk fall setup time t dsi figure 6 (note 2) 10 ns q-dac data to clk rise setup time t dsq figure 6 (note 2) 10 ns clk fall to i-dac data hold time t dhi figure 6 (note 2) 0 ns clk rise to q-dac data hold time t dhq figure 6 (note 2) 0 ns clk duty cycle 50 % clk duty-cycle variation ?5 % digital output rise/fall time 20% to 80% 2.5 ns serial-interface timing characteristics (figure 7, note 2) falling edge of cs to rising edge of first sclk time t css 10 ns din to sclk setup time t ds 10 ns din to sclk hold time t dh 0ns sclk pulse-width high t ch 25 ns sclk pulse-width low t cl 25 ns sclk period t cp 50 ns sclk to cs setup time t cs 10 ns cs high pulse width t csw 80 ns cs high to dout active high t csd bit ad0 set 200 ns
max19708 10-bit, 11msps, ultra-low-power analog front-end 8 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 11mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units cs high to dout low (aux-adc conversion time) t conv bit ad0 set, no averaging (see table 15), f clk = 11mhz, clk divider = 4 (see table 16) 4.36 ? dout low to cs setup time t dcs bit ad0, ad10 set 200 ns sclk low to dout data out t cd bit ad0, ad10 set 14.5 ns cs high to dout high impedance t chz bit ad0, ad10 set 200 ns mode-recovery timing characteristics (figure 8) from shutdown to rx mode, adc settles to within 1db sinad 82.2 shutdown wake-up time t wake , sd from shutdown to tx mode, dac settles to within 10 lsb error 29 ? fr om i d l e to rx m od e w i th c lk p r esent d ur i ng i d l e, ad c settl es to w i thi n 1d b s in ad 9.6 idle wake-up time (with clk) t wake , st0 from idle to tx mode with clk present during idle, dac settles to 10 lsb error 7.6 ? from standby to rx mode, adc settles to within 1db sinad 17.5 standby wake-up time t wake , st1 from standby to tx mode, dac settles to 10 lsb error 24 ? enable time from tx to rx (ext2-tx to ext2-rx, ext4-tx to ext4-rx, and spi4-tx to spi3-rx states) t enable , rx adc settles to within 1db sinad 500 ns e nab l e ti m e fr om rx to tx ( e xt1- rx to e xt1- tx, e xt4- rx to e xt4- tx, and s p i3- rx to s p i4- tx s tates) t enable , tx dac settles to within 10 lsb error 500 ns enable time from tx to rx (ext1-tx to ext1-rx, ext3-tx to ext3-rx, and spi1-tx to spi1-rx states) t enable , rx adc settles to within 1db sinad 8.1 ? e nab l e ti m e fr om rx to tx ( e xt2- rx to e xt2- tx, e xt3- rx to e xt3- tx, and s p i1- rx to s p i2- tx s tates) t enable , tx dac settles to within 10 lsb error 7.0 ? internal reference (v refin = v dd ; v refp , v refn , v com levels are generated internally) positive reference v refp - v com 0.256 v negative reference v refn - v com -0.256 v common-mode output voltage v com v dd / 2 - 0.15 v dd / 2 v dd / 2 + 0.15 v maximum refp/refn/com source current i source 2ma
max19708 10-bit, 11msps, ultra-low-power analog front-end _______________________________________________________________________________________ 9 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 11mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, unless otherwise noted. c l < 5pf on all aux-dac outputs. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units maximum refp/refn/com sink current i sink 2ma differential reference output v ref v refp - v refn +0.460 +0.512 +0.548 v differential reference temperature coefficient reftc ?8 ppm/? buffered external reference (external v refin = 1.024v applied; v refp , v refn , v com levels are generated internally) reference input voltage v refin 1.024 v differential reference output v diff v refp - v refn 0.512 v common-mode output voltage v com v dd / 2 v maximum refp/refn/com source current i source 2ma maximum refp/refn/com sink current i sink 2ma refin input current -0.7 ? refin input resistance 500 k digital inputs (clk, sclk, din, cs , d0?9, t/ r , shdn ) input high threshold v inh 0.7 x ov dd v input low threshold v inl 0.3 x ov dd v input leakage di in d0?9, clk, sclk, din, cs , t/ r , shdn = ognd or ov dd -1 +1 ? input capacitance dc in 5pf digital outputs (d0?9, dout) output-voltage low v ol i sink = 200? 0.2 x ov dd v output-voltage high v oh i source = 200? 0.8 x ov dd v tri-state leakage current i leak -1 +1 ? tri-state output capacitance c out 5pf note 1: specifications from t a = +25? to +85? are guaranteed by production tests. specifications from t a = +25? to -40? are guaranteed by design and characterization. note 2: guaranteed by design and characterization. note 3: the minimum clock frequency (f clk ) for the max19708 is 1.5mhz (typ). the minimum aux-adc sample rate clock frequen- cy (aclk) is determined by f clk and the chosen aux-adc clock-divider value. the minimum aux-adc aclk > 1.5mhz / 128 = 11.7khz. the aux-adc conversion time does not include the time to clock the serial data out of the spi. the maximum conversion time (for no averaging, navg = 1) will be t conv (max) = (12 x 1 x 128) / 1.5mhz = 1024?. note 4: snr, sinad, sfdr, hd3, and thd are based on a differential analog input voltage of -0.5dbfs referenced to the amplitude of the digital outputs. sinad and thd are calculated using hd2 through hd6. note 5: crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. ffts are performed on each channel. the parameter is specified as the power ratio of the first and second channel fft test tone. note 6: amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output signals using a sine-wave fit.
max19708 10-bit, 11msps, ultra-low-power analog front-end 10 ______________________________________________________________________________________ rx adc channel-ia fft plot max19708 toc01 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 1.1 2.2 3.3 4.4 5.5 f ia = 1.882886mhz hd2 hd3 rx adc channel-qa fft plot max19708 toc02 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 1.1 2.2 3.3 4.4 5.5 f qa = 1.882886mhz hd2 hd3 rx adc channel-ia two-tone fft plot max19708 toc03 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 1.1 2.2 3.3 4.4 5.5 f 1 = 1.885mhz f 2 = 1.985mhz a ia = -7dbfs per tone 4096-point data record f 2 f 1 rx adc channel-qa two-tone fft plot max19708 toc04 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 1.1 2.2 3.3 4.4 5.5 f 1 = 1.885mhz f 2 = 1.985mhz a ia = -7dbfs per tone 4096-point data record f 2 f 1 rx adc signal-to-noise ratio vs. analog input frequency max19708 toc05 analog input frequency (mhz) snr (db) 47 49 51 53 55 57 45 0 102030405060708090100 qa ia rx adc signal-to-noise and distortion ratio vs. analog input frequency max19708 toc06 analog input frequency (mhz) sinad (db) 51 53 55 57 0 102030405060708090100 qa ia 49 47 45 rx adc total harmonic distortion vs. analog input frequency max19708 toc07 analog input frequency (mhz) thd (db) -66 -68 -70 -72 -74 -76 -78 -64 -80 0 102030405060708090100 ia qa rx adc spurious-free dynamic range vs. analog input frequency max19708 toc08 analog input frequency (mhz) sfdr (dbc) 55 60 65 70 75 80 50 0 102030405060708090100 qa ia 20 25 30 35 40 45 50 55 60 -25 -20 -15 -10 -5 0 rx adc signal-to-noise ratio vs. analog input amplitude max19708 toc09 analog input amplitude (dbfs) snr (db) f in = 1.875mhz ia qa typical operating characteristics (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 11mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
max19708 10-bit, 11msps, ultra-low-power analog front-end ______________________________________________________________________________________ 11 20 25 30 35 40 45 50 55 60 -25 -20 -15 -10 -5 0 rx adc signal-to-noise and distortion ratio vs. analog input amplitude max19708 toc10 analog input amplitude (dbfs) sinad (db) f in = 1.875mhz ia qa 40 45 50 55 60 65 70 75 80 -25 -20 -15 -10 -5 0 rx adc spurious-free dynamic range vs. analog input amplitude max19708 toc11 analog input amplitude (dbfs) sfdr (dbc) f in = 1.875mhz qa ia 53.0 53.5 54.0 54.5 55.0 55.5 56.0 24 3 567891011 rx adc signal-to-noise ratio vs. sampling rate max19708 toc12 sampling rate (mhz) snr (db) f in = 1.875mhz qa ia 52.0 56.5 56.0 55.5 54.5 55.0 54.0 53.5 53.0 52.5 57.0 24 3 567891011 rx adc signal-to-noise and distortion ratio vs. sampling rate max19708 toc13 sampling rate (mhz) sinad (db) f in = 1.875mhz qa ia 66 78 76 74 72 70 68 80 24 3 567891011 rx adc spurious-free dynamic range vs. sampling rate max19708 toc14 sampling rate (mhz) sfdr (dbc) ia qa f in = 1.875mhz 52.0 53.5 53.0 52.5 54.0 54.5 55.0 55.5 56.0 56.5 57.0 35 45 40 50 55 60 65 rx adc signal-to-noise ratio vs. clock duty cycle max19708 toc15 clock duty cycle (%) snr (db) f in = 1.875mhz qa ia 52.0 53.5 53.0 52.5 54.0 54.5 55.0 55.5 56.0 56.5 57.0 35 45 40 50 55 60 65 rx adc signal-to-noise and distortion ratio vs. clock duty cycle max19708 toc16 clock duty cycle (%) sinad (db) f in = 1.875mhz qa ia 60 66 64 62 68 70 72 74 76 78 80 35 45 40 50 55 60 65 rx adc spurious-free dynamic range vs. clock duty cycle max19708 toc17 clock duty cycle (%) sfdr (dbc) ia f in = 1.875mhz qa -1.00 -0.50 -0.75 -0.25 0 0.25 0.50 0.75 1.00 -40 10 -15 356085 rx adc offset error vs. temperature max19707 toc18 temperature ( c) offset error (%fs) ia qa typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 11mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
max19708 10-bit, 11msps, ultra-low-power analog front-end 12 ______________________________________________________________________________________ 30 45 40 35 50 55 60 65 70 75 80 -30 -25 -20 -15 -10 -5 0 tx path spurious-free dynamic range vs. output amplitude max19708 toc22 output amplitude (dbfs) sfdr (dbc) f out = 620khz qa ia 0 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 -40 10 -15 356085 rx adc gain error vs. temperature max19708 toc19 temperature ( c) gain error (%fs) qa ia 67 76 75 74 72 73 71 70 69 68 77 24 3 567891011 tx path spurious-free dynamic range vs. sampling rate max19708 toc20 sampling rate (mhz) sfdr (dbc) id qd f out = 617khz 63.0 68.0 65.5 73.0 70.5 75.5 78.0 100 200 300 400 500 600 700 800 tx path spurious-free dynamic range vs. output frequency max19708 toc21 output frequency (mhz) sfdr (dbc) id qd tx path channel-id spectral plot max19708 toc23 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0.20 0.73 1.26 1.79 2.32 2.85 3.38 3.91 4.44 4.97 5.50 f id = 617khz tx path channel-qd spectral plot max19708 toc24 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0.20 0.73 1.26 1.79 2.32 2.85 3.38 3.91 4.44 4.97 5.50 f qd = 617khz tx path channel-id spectral plot with image rejection max19708 toc25 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0.200 1.184 1.676 0.692 2.168 2.660 3.152 3.644 4.136 4.628 5.120 f id = 800khz, f clk = 5.12mhz image rejection tx path channel-id two-tone spectral plot max19708 toc26 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0.20 0.73 1.26 1.79 2.32 2.85 3.38 3.91 4.44 4.97 5.50 f 1 = 560khz, f 2 = 660khz tx path channel-qd two-tone spectral plot max19708 toc27 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0.20 0.73 1.26 1.79 2.32 2.85 3.38 3.91 4.44 4.97 5.50 f 1 = 560khz, f 2 = 660khz typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 11mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
max19708 10-bit, 11msps, ultra-low-power analog front-end ______________________________________________________________________________________ 13 10.0 13.0 12.5 12.0 11.5 11.0 10.5 13.5 24 3 567891011 supply current vs. sampling rate max19708 toc28 sampling rate (mhz) supply current (ma) ext4 mode i vdd tx mode i vdd rx mode rx adc integral nonlinearity max19708 toc29 digital output code inl (lsb) 896 768 512 640 256 384 128 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 1.00 -1.00 0 1024 transmit filter frequency response max19708 toc30 frequency (mhz) amplitude (db) 1 -60 -80 -40 -20 0 -100 0.1 10 tx path integral nonlinearity max19708 toc31 digital input code inl (lsb) 896 768 512 640 256 384 128 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0.8 -0.8 0 1024 tx path differential nonlinearity max19707 toc32 digital input code dnl (lsb) 896 768 512 640 256 384 128 -0.60 -0.45 -0.30 -0.15 0 0.15 0.30 0.45 0.60 0.75 -0.75 01024 transmit filter passband ripple max19708 toc34 frequency (mhz) amplitude (db) 1.2 0.9 0.6 0.3 -0.10 -0.04 0 -0.06 -0.12 -0.08 -0.02 0.02 0.04 -0.14 0 aux-dac integral nonlinearity max19708 toc35 digital input code inl (lsb) 3072 2048 1024 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 04096 aux-dac differential nonlinearity max19708 toc36 digital input code dnl (lsb) 3072 2048 1024 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 -0.8 0 4096 typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 11mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.) reference output voltage vs. temperature max19708 toc33 temperature ( c) v refp - v refn (v) 85 60 -15 10 35 0.505 0.510 0.515 0.520 0.500 -40 v refp - v refn
max19708 10-bit, 11msps, ultra-low-power analog front-end 14 ______________________________________________________________________________________ pin name function 1 refp upper reference voltage. bypass with a 0.33? capacitor to gnd as close to refp as possible. 2, 8, 11, 31, 33, 39, 43 v dd analog supply voltage. bypass v dd to gnd with a combination of a 2.2? capacitor in parallel with a 0.1? capacitor. 3 iap channel-ia positive analog input. for single-ended operation, connect signal source to iap. 4 ian channel-ia negative analog input. for single-ended operation, connect ian to com. 5, 7, 12, 32, 42 gnd analog ground. connect all gnd pins to ground plane. 6 clk conversion clock input. clock signal for both receive adcs and transmit dacs. 9 qan channel-qa negative analog input. for single-ended operation, connect qan to com. pin description aux-adc integral nonlinearity max19708 toc37 digital output code inl (lsb) 896 768 512 640 256 384 128 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 2.0 -2.0 0 1024 aux-adc differential nonlinearity max19708 toc38 digital output code dnl (lsb) 896 768 512 640 256 384 128 -0.4 0 0.4 0.8 -0.8 0 1024 aux-dac output voltage vs. output source current max19708 toc39 output source current (ma) output voltage (v) 10 1 0.1 0.01 0.5 1.0 1.5 2.0 2.5 3.0 0 0.001 100 aux-dac output voltage vs. output sink current max19708 toc40 output sink current (ma) output voltage (v) 10 1 0.1 0.01 0.5 1.0 1.5 2.0 2.5 3.0 0 0.001 100 aux-dac settling time max19708 toc41 500ns/div 500mv/div step from 1/4fs to 3/4fs typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 11mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
max19708 10-bit, 11msps, ultra-low-power analog front-end ______________________________________________________________________________________ 15 pin name function 10 qap channel-qa positive analog input. for single-ended operation, connect signal source to qap. 13?8, 21?4 d0?9 digital i/o. outputs for receive adc in rx mode. inputs for transmit dac in tx mode. d9 is the most significant bit (msb) and d0 is the least significant bit (lsb). 19 ognd output-driver ground 20 ov dd output-driver power supply. supply range from +1.8v to v dd . bypass ov dd to ognd with a combination of a 2.2? capacitor in parallel with a 0.1? capacitor. 25 shdn active-low shutdown input. apply logic-low to place the max19708 in shutdown. 26 dout aux-adc digital output 27 t/ r transmit- or receive-mode select input. t/ r logic-low input sets the device in receive mode. a logic-high input sets the device in transmit mode. 28 din 3-wire serial-interface data input. data is latched on the rising edge of the sclk. 29 sclk 3-wire serial-interface clock input 30 cs 3-wire serial-interface chip-select input. logic-low enables the serial interface. 34 adc2 analog input for auxiliary adc 35 adc1 analog input for auxiliary adc 36 dac3 analog output for auxiliary dac3 37 dac2 analog output for auxiliary dac2 38 dac1 analog output for auxiliary dac1 (afc dac, v out = 1.1v during power-up) 40, 41 idn, idp tx path channel-id differential voltage output 44, 45 qdn, qdp tx path channel-qd differential voltage output 46 refin reference input. connect to v dd for internal reference. 47 com common-mode voltage i/o. bypass com to gnd with a 0.33? capacitor. 48 refn negative reference i/o. rx adc conversion range is ?v refp - v refn ). bypass refn to gnd with a 0.1? capacitor. ep exposed paddle. exposed paddle is internally connected to gnd. connect ep to the gnd plane. pin description (continued) spi is a trademark of motorola, inc. microwire is a trademark of national semiconductor corp. detailed description the max19708 integrates a dual, 10-bit rx adc and a dual, 10-bit tx dac with td-scdma baseband filters while providing ultra-low power and high dynamic per- formance at 11msps conversion rate. the rx adc ana- log input amplifiers are fully differential and accept 1.024v p-p full-scale signals. the tx dac analog out- puts are fully differential with ?10mv or ?00mv full- scale output, selectable common-mode dc level, and adjustable i/q offset trim. the max19708 integrates three 12-bit auxiliary dac (aux-dac) channels and a 10-bit, 333ksps auxiliary adc (aux-adc) with 4:1 input multiplexer. the aux-dac channels feature 1s settling time for fast agc, vga, and afc level setting. the aux-adc features data aver- aging to reduce processor overhead and a selectable clock-divider to program the conversion rate. the max19708 includes a 3-wire serial interface to control operating modes and power management. the serial interface is spi and microwire compatible. the max19708 serial interface selects shutdown, idle, standby, transmit (tx), and receive (rx) modes, as well as controlling aux-dac and aux-adc channels. the rx adc and tx dac share a common digital i/o to reduce the digital interface to a single 10-bit parallel multiplexed bus. the 10-bit digital bus operates on a single +1.8v to +3.3v supply.
max19708 10-bit, 11msps, ultra-low-power analog front-end 16 ______________________________________________________________________________________ figure 1. rx adc internal t/h circuits s3b s3a com s5b s5a qap qan s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com hold hold clk internal nonoverlapping clock signals track track s2a s2b s3b s3a com s5b s5a iap ian s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com s2a s2b max19708 dual 10-bit rx adc the adc uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. samples taken at the inputs move progressively through the pipeline stages every half clock cycle. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel ia and 5.5 clock cycles for channel qa. the adc full-scale analog input range is ? ref with a v dd / 2 (?.2v) common-mode input range. v ref is the difference between v refp and v refn . see the reference configurations section for details. input track-and-hold (t/h) circuits figure 1 displays a simplified diagram of the rx adc input track-and-hold (t/h) circuitry. both adc inputs (iap, qap, ian, and qan) can be driven either differen- tially or single-ended. match the impedance of iap and ian, as well as qap and qan, and set the input signal common-mode voltage within the v dd / 2 (?00mv) rx adc range for optimum performance.
max19708 10-bit, 11msps, ultra-low-power analog front-end ______________________________________________________________________________________ 17 rx adc system timing requirements figure 3 shows the relationship between the clock, ana- log inputs, and the resulting output data. channel i (chi) and channel q (chq) are sampled on the rising edge of the clock signal (clk) and the resulting data is multiplexed at the d0?9 outputs. chi data is updated on the rising edge and chq data is updated on the falling edge of the clk. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for chi and 5.5 clock cycles for chq. digital input/output data (d0?9) d0?9 are the rx adc digital logic outputs when the max19708 is in receive mode. this bus is shared with the tx dac digital logic inputs and operates in half- duplex mode. d0?9 are the tx dac digital logic inputs when the max19708 is in transmit mode. the logic level is set by ov dd from 1.8v to v dd . the digital output cod- ing is offset binary (table 1). keep the capacitive load on the digital outputs d0?9 as low as possible (< 15pf) to avoid large digital currents feeding back into the analog portion of the max19708 and degrading its dynamic performance. buffers on the digital outputs iso- late the outputs from heavy capacitive loads. adding 100 resistors in series with the digital outputs close to the max19708 will help improve adc performance. refer to the max19708evkit schematic for an example of the digital outputs driving a digital buffer through 100 series resistors. during shdn, idle, and stby states, d0?9 are inter- nally pulled up to prevent floating digital inputs. to ensure no current flows through d0?9 i/o, the external bus needs to be either tri-stated or pulled up to ov dd and should not be pulled to ground. table 1. rx adc output codes vs. input voltage differential input voltage differential input (lsb) offset binary (d0?9) output decimal code v ref x 512/512 511 (+full scale - 1 lsb) 11 1111 1111 1023 v ref x 511/512 510 (+full scale - 2 lsb) 11 1111 1110 1022 v ref x 1/512 +1 10 0000 0001 513 v ref x 0/512 0 (bipolar zero) 10 0000 0000 512 -v ref x 1/512 -1 01 1111 1111 511 -v ref x 511/512 -511 (-full scale +1 lsb) 00 0000 0001 1 -v ref x 512/512 -512 (-full scale) 00 0000 0000 0 figure 2. rx adc transfer function input voltage (lsb) -1 -510 -509 1024 2 x v ref 1 lsb = v ref = v refp - v refn v ref v ref v ref v ref 0+ 1 -511 +510 +512 +511 -512 +509 (com) (com) offset binary output code (lsb) 00 0000 0000 00 0000 0001 00 0000 0010 00 0000 0011 11 1111 1111 11 1111 1110 11 1111 1101 01 1111 1111 10 0000 0000 10 0000 0001
max19708 10-bit, 11msps, ultra-low-power analog front-end 18 ______________________________________________________________________________________ figure 3. rx adc system timing diagram t doq t cl t ch t clk t doi 5 clock-cycle latency (chi) 5.5 clock-cycle latency (chq) d0?9 d0q d1i d1q d2i d2q d3i d3q d4i d4q d5i d5q d6i d6q chi chq clk table 2. tx path output voltage vs. input codes (internal reference mode v refdac = 1.024v, external reference mode v refdac = v refin ; v fs = 410 for 820mv p-p full scale and v fs = 500 for 1v p-p full scale) differential output voltage (v) offset binary (d0?9) input decimal code 11 1111 1111 1023 11 1111 1110 1022 10 0000 0001 513 10 0000 0000 512 01 1111 1111 511 00 0000 0001 1 00 0000 0000 0 v v fs refdac 1024 1023 1023 () v v fs refdac 1024 1021 1023 () v v fs refdac 1024 3 1023 () v v fs refdac 1024 1 1023 () v v fs refdac 1024 1 1023 () ? v v fs refdac 1024 1021 1023 () ? v v fs refdac 1024 1023 1023 () ? dual 10-bit tx dac and transmit path the dual 10-bit digital-to-analog converters (tx dac) operate with clock speeds up to 11mhz. the tx dac digital inputs, d0?9, are multiplexed on a single 10-bit bus. the voltage reference determines the tx path full- scale voltage at idp, idn and qdp, qdn analog out- puts. see the reference configurations section for setting reference voltage. each tx path output channel integrates a lowpass filter tuned to meet the td-scdma spectral mask requirements. the td-scdma filters are tuned for 1.32mhz cutoff fre- quency and > 55db image rejection at f image = 4.32mhz, f out = 800khz, and f clk = 5.12mhz. see figure 4 for an illustration of the filter frequency response. buffer amplifiers follow the td-scdma filters. the amplifi- er outputs (idn, idp, qdn, qdp) are biased at an adjustable common-mode dc level and designed to drive a differential input stage with 70k input imped- ance. this simplifies the analog interface between rf
max19708 10-bit, 11msps, ultra-low-power analog front-end ______________________________________________________________________________________ 19 quadrature upconverters and the max19708. many rf upconverters require a 0.9v to 1.4v common-mode bias. the max19708 common-mode dc bias eliminates dis- crete level-setting resistors and code-generated level shifting while preserving the full dynamic range of each tx dac. the tx dac differential analog outputs cannot be used in single-ended mode because of the internally generated common-mode dc level. table 2 shows the tx path output voltage vs. input codes. table 11 shows the selection of dc common-mode levels. see figure 5 for an illustration of the tx dac analog output levels. the buffer amplifiers also feature a programmable full- scale output level of ?10mv or ?00mv and indepen- dent dc offset trim on each i/q channel. both features are configured through the spi interface. the dc offset correction is used to optimize sideband and carrier sup- pression in the tx signal path (see tables 8 and 10). tx dac timing figure 6 shows the relationship between the clock, input data, and analog outputs. data for the i channel (id) is latched on the falling edge of the clock signal, and q- channel (qd) data is latched on the rising edge of the clock signal. both i and q outputs are simultaneously updated on the next rising edge of the clock signal. 3-wire serial interface and operation modes the 3-wire serial interface controls the max19708 oper- ation modes as well as the three 12-bit aux-dacs and the 10-bit aux-adc. upon power-up, program the max19708 to operate in the desired mode. use the 3- wire serial interface to program the device for shutdown, idle, standby, rx, tx, aux-dac controls, or aux-adc conversion. a 16-bit data register sets the mode control as shown in table 3. the 16-bit word is composed of a3?0 control bits and d11?0 data bits. data is shifted in msb first (d11) and lsb last (a0). tables 4, 5, and 6 show the max19708 operating modes and spi com- mands. the serial interface remains active in all modes. spi register description program the control bits, a3?0, in the register as shown in table 3 to select the operating mode. modify a3?0 bits to select from enable-16, aux-dac1, aux-dac2, aux-dac3, ioffset, qoffset, aux-adc, enable-8, and comsel modes. enable-16 is the default operat- ing mode. this mode allows for shutdown, idle, and standby states as well as switching between fast, slow, rx and tx modes. table 4 shows the max19708 power-management modes. table 5 shows the t/ r pin- controlled external tx-rx switching modes. table 6 shows the spi-controlled tx-rx switching modes. figure 4. td-scdma filter frequency response 0.8 channel edge 4.32 image 1.27 f c 5.12 f clk freq (mhz) not to scale -49.3db -15db -3db 0db -55db (min) -57.1db occupied channel amplitude td-scdma filter response dac sin(x)/x response tx path: sfdr = 73dbc thd = -71db snr = 56.5db
max19708 10-bit, 11msps, ultra-low-power analog front-end 20 ______________________________________________________________________________________ figure 6. tx dac system timing diagram t dsq t dsi q: n - 2 i: n - 1 d0?9 clk id qd q: n - 1 i: n q: n i: n + 1 n - 2 n - 1 n n - 2 n - 1 n t dhq t dhi figure 5. tx dac common-mode dc level at idn, idp or qdn, qdp differential outputs 0 full scale = 1.305v v com = 1.10v zero scale = 0.895v 0v common-mode level select cm1 = 1, cm0 = 0 v com = 1.10v v diff = 410mv example: tx rfic input requirements ?dc common-mode bias = 1.0v (min), 1.2v (typ) ?baseband input = 410mv dc-coupled 90 max19708 filter tx dac i-ch filter tx dac q-ch
max19708 10-bit, 11msps, ultra-low-power analog front-end ______________________________________________________________________________________ 21 table 4. power-management modes address data bits t/ r a3 a2 a1 a0 e9* e3 e2 e1 e0 pin 27 mode function (power management ) description comment 1x000 x shdn shutdown rx adc = off tx dac = off aux-dac = off aux-adc = off clk = off ref = off device is in complete shutdown. overrides t/ r pin. xx001 x idle idle rx adc = off tx dac = off aux-dac = last state clk = on ref = on fast turn-on time. moderate idle power. overrides t/ r pin. 0000 (16-bit mode) or 1000 (8-bit mode) 1x010 x stby standby rx adc = off tx dac = off aux-dac = last state aux-adc = off clk = off ref = on slow turn-on time. low standby power. overrides t/ r pin. x = don? care. * bit e9 is not available in 8-bit mode. table 3. max19708 mode control d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a3 a2 a1 a0 register name (msb) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (lsb) enable-16 e11 = 0 reserved e10 = 0 reserved e9e7e6e5e4e3e2e1e0000 0 aux-dac1 1d11 1d10 1d9 1d8 1d7 1d6 1d5 1d4 1d3 1d2 1d1 1d0 0 0 0 1 aux-dac2 2d11 2d10 2d9 2d8 2d7 2d6 2d5 2d4 2d3 2d2 2d1 2d0 0 0 1 0 aux-dac3 3d11 3d10 3d9 3d8 3d7 3d6 3d5 3d4 3d3 3d2 3d1 3d0 0 0 1 1 ioffset io5 io4 io3 io2 io1 io0 0 1 0 0 qoffset qo5 qo4 qo3 qo2 qo1 qo0 0 1 0 1 comsel cm1 cm0 0 1 1 0 aux-adc ad11 = 0 reserved ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 0 1 1 1 enable-8 e3 e2 e1 e0 1 0 0 0 ?= not used.
max19708 10-bit, 11msps, ultra-low-power analog front-end 22 ______________________________________________________________________________________ table 5. external tx-rx control using t/ r pin (t/ r = 0 = rx mode, t/ r = 1 = tx mode) address data bits t/ r a3 a2 a1 a0 e3 e2 e1 e0 pin 27 state function rx to tx-tx to rx switching speed description comment 0 ext1-rx rx mode: rx adc = on tx dac = on rx bus = enable moderate power: fast rx to tx when t/ r transitions 0 to 1. 0011 1 ext1-tx fast-slow tx mode: rx adc = off tx dac = on tx bus = enable low power: slow tx to rx when t/ r transitions 1 to 0. 0 ext2-rx (default) rx mode: rx adc = on tx dac = off rx bus = enable low power: slow rx to tx when t/ r transitions 0 to 1. 0100 1 ext2-tx slow-fast tx mode: rx adc = on tx dac = on tx bus = enable moderate power: fast tx to rx when t/ r transitions 1 to 0. 0 ext3-rx rx mode: rx adc = on tx dac = off rx bus = enable low power: slow rx to tx when t/ r transitions 0 to 1. 0101 1 ext3-tx slow-slow tx mode: rx adc = off tx dac = on tx bus = enable low power: slow tx to rx when t/ r transitions 1 to 0. 0 ext4-rx rx mode: rx adc = on tx dac = on rx bus = enable moderate power: fast rx to tx when t/ r transitions 0 to 1. 0000 (16-bit mode) or 1000 (8-bit mode) 0110 1 ext4-tx fast-fast tx mode: rx adc = on tx dac = on tx bus = enable moderate power: fast tx to rx when t/ r transitions 1 to 0. in enable-16 mode, the aux-dacs have independent control bits e4, e5, and e6, bit e7 sets the tx path full- scale ouputs, and bit e9 enables the aux-adc. table 7 shows the auxiliary dac enable codes. table 8 shows the full-scale output selection. table 9 shows the auxil- iary adc enable code. bits e11 and e10 are reserved. program bits e11 and e10 to logic-low. modes aux-dac1, aux-dac2, and aux-dac3 select the aux-dac channels named dac1, dac2, and dac3 and hold the data inputs for each dac. bits _d11?d0
max19708 10-bit, 11msps, ultra-low-power analog front-end ______________________________________________________________________________________ 23 are the data inputs for each aux-dac and can be pro- grammed through spi. the max19708 also includes two 6-bit registers that can be programmed to adjust the offsets for the tx path i and q channels indepen- dently (see table 10). use the comsel mode to select the output common-mode voltage with bits cm1 and cm0 (see table 11). use aux-adc mode to start the auxiliary adc conversion (see the 10-bit, 333ksps auxiliary adc section for details). use enable-8 mode for faster enable and switching between shut- down, idle, and standby states as well as switching between fast, slow, rx and tx modes. shutdown mode offers the most dramatic power sav- ings by shutting down all the analog sections of the max19708 and placing the rx adc digital outputs in table 6. tx-rx control using spi commands address data bits t/ r a3 a2 a1 a0 e3 e2 e1 e0 pin 27 mode function (tx-rx switching speed) description comments 1011 x spi1-rx slow rx mode: rx adc = on tx dac = off rx bus = enable low power: slow rx to tx through spi command. 1100 x spi2-tx slow tx mode: rx adc = off tx dac = on tx bus = enable low power: slow tx to rx through spi command. 1101 x spi3-rx fast rx mode: rx adc = on tx dac = on rx bus = enabled moderate power: fast rx to tx through spi command. 0000 (16-bit mode) or 1000 (8-bit mode) 1110 x spi4-tx fast tx mode: rx adc = on tx dac = on tx bus = enabled moderate power: fast tx to rx through spi command. table 7. aux-dac enable table (enable-16 mode) e6 e5 e4 aux-dac3 aux-dac2 aux-dac1 0 00 on on on 0 01 on on off 0 10 on off on 0 11 on off off 1 00 off on on 1 01 off on off 1 10 off off on 1 11 off off off x = don? care. table 8. tx path full-scale select (enable-16 mode) e7 tx-path output full scale 0 (default) ?10mv 1 ?00mv table 9. aux-adc enable table (enable-16 mode) e9 selection 0 (default) aux-adc is powered on 1 aux-adc is powered off
max19708 10-bit, 11msps, ultra-low-power analog front-end 24 ______________________________________________________________________________________ tri-state mode. when the rx adc outputs transition from tri-state to on, the last converted word is placed on the digital outputs. the tx dac previously stored data is lost when coming out of shutdown mode. the wake-up time from shutdown mode is dominated by the time required to charge the capacitors at refp, refn, and com. in internal reference mode and buffered external reference mode, the wake-up time is typically 82.2? to enter rx mode and 29? to enter tx mode. in idle mode, the reference and clock distribution cir- cuits are powered, but all other functions are off. the rx adc outputs are forced to tri-state. the wake-up time is 9.6? to enter rx mode and 7.6? to enter tx mode. when the rx adc outputs transition from tri- state to on, the last converted word is placed on the digital outputs. in standby mode, the reference is powered, but the rest of the device functions are off. the wake-up time from standby mode is 17.5? to enter rx mode and 24? to enter tx mode. when the rx adc outputs transition from tri-state to active, the last converted word is placed on the digital outputs. fast and slow rx and tx modes in addition to the external tx-rx control, the max19708 also features slow and fast modes for switching between rx and tx operation. in fast tx mode, the rx adc core is powered on but the adc core digital out- puts are tri-stated on the d0?9 bus; likewise, in fast rx mode, the transmit path (dac core and tx filter) is powered on but the dac core digital inputs are tri-stat- ed on the d0?9 bus. the switching time between tx to rx or rx to tx is fast because the converters are on and do not have to recover from a power-down state. in fast mode, the switching time between rx to tx and tx to rx is 0.5?. however, power consumption is higher table 10. offset control bits for i and q channels (ioffset or qoffset mode) bits io5?o0 when in ioffset mode, bits qo5?o0 when in qoffset mode io5/qo5 io4/qo4 io3/qo3 io2/qo2 io1/qo1 io0/qo0 offset 1 lsb = (vfs p-p / 1023) 1 1 1 1 1 1 -31 lsb 1 1 1 1 1 0 -30 lsb 1 1 1 1 0 1 -29 lsb 100010-2 lsb 100001-1 lsb 1000000mv 0 0 0 0 0 0 0mv (default) 0000011 lsb 0000102 lsb 01110129 lsb 01111030 lsb 01111131 lsb note: for transmit full-scale select of ?10mv: 1 lsb = (820mv p-p / 1023) = 0.8016mv. for transmit full scale select of ?00mv: 1 lsb = (1v p-p / 1023) = 0.9775mv. table 11. common-mode select (comsel mode) cm1 cm0 tx path output common mode (v) 0 0 1.40 (default) 0 1 1.25 1 0 1.10 1 1 0.90
max19708 10-bit, 11msps, ultra-low-power analog front-end ______________________________________________________________________________________ 25 in this mode because both the tx and rx cores are always on. to prevent bus contention in these states, the rx adc output buffers are tri-stated during tx and the tx dac input bus is tri-stated during rx. in slow mode, the rx adc core is off during tx; like- wise the tx dac and filters are turned off during rx to yield lower power consumption in these modes. for example, the power in slow tx mode is 35.1mw. the power consumption during rx is 24mw compared to 41.1mw power consumption in fast mode. however, the recovery time between states is increased. the switching time in slow mode between rx to tx is 7s and tx to rx is 8.1?. external t/ r r switching control vs. serial-interface control bit e3 in the enable-16 or enable-8 register deter- mines whether the device tx-rx mode is controlled externally through the t/ r input (e3 = low) or through the spi command (e3 = high). by default, the max19708 is in the external tx-rx control mode. in the external control mode, use the t/ r input (pin 27) to switch between rx and tx modes. using the t/ r pin provides faster switch- ing between rx and tx modes. to override the external tx-rx control, program the max19708 through the serial interface. during shdn, idle, or stby modes, the t/ r input is overridden. to restore external tx-rx control, program bit e3 low and exit the shdn, idle, or stby modes through the serial interface. spi timing the serial digital interface is a standard 3-wire connec- tion ( cs , sclk, din) compatible with spi/qspi/ microwire/dsp interfaces. set cs low to enable the serial data loading at din or output at dout. following a cs high-to-low transition, data is shifted synchronously, most significant bit first, on the rising edge of the serial clock (sclk). after 16 bits are loaded into the serial input register, data is transferred to the latch when cs transitions high. cs must transition high for a minimum of 80ns before the next write sequence. the sclk can idle either high or low between transitions. figure 7 shows the detailed timing diagram of the 3-wire serial interface. figure 7. serial-interface timing diagram 16-bit or 8-bit write into spi (din) 16-bit or 8-bit write into spi during aux-adc conversion 10-bit read out of aux-adc (dout) with simultaneous 16-bit write into spi (din) t chz lsb bit a0 (din) bit d1 (din) lsb msb bit d10 (din) lsb a0 dout = tri-stated when aux-adc is idle dout = active when bit ad0 is set aux-adc is busy aux-adc data ready msb bit d9 (dout) lsb bit d0 (dout) lsb bit d0 (held) dout tri- stated bit ad0 cleared d10 (16-bit) d2 (8-bit) msb d11 (16-bit) d3 (8-bit) msb bit d11 (din) t dcs t conv t csd t cs t cp t css t csw t ds t ch t cl t dh t cd sclk cs din dout qspi is a trademark of motorola, inc.
max19708 10-bit, 11msps, ultra-low-power analog front-end 26 ______________________________________________________________________________________ mode-recovery timing figure 8 shows the mode-recovery timing diagram. t wake is the wakeup time when exiting shutdown, idle, or standby mode and entering rx or tx mode. t enable is the recovery time when switching between either rx or tx mode. t wake or t enable is the time for the rx adc to settle within 1db of specified sinad performance and tx dac settling to 10 lsb error. t wake and t enable times are measured after either the 16-bit serial com- mand is latched into the max19708 by a cs transition high (spi controlled) or a t/ r logic transition (external tx-rx control). in fast mode, the recovery time is 0.5? to switch between tx or rx modes. system clock input (clk) both the rx adc and tx dac share the clk input. the clk input accepts a cmos-compatible signal level set by ov dd from 1.8v to v dd . since the interstage con- version of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). specifically, sampling occurs on the rising edge of the clock signal, requiring this edge to provide the lowest possible jitter. any significant clock jitter limits the snr performance of the on-chip rx adc as follows: where f in represents the analog input frequency and t aj is the time of the clock jitter. clock jitter is especially critical for undersampling applications. consider the clock input as an analog input and route away from any analog input or other digital signal lines. the max19708 clock input operates with an ov dd / 2 voltage threshold and accepts a 50% ?5% duty cycle. log snr ft = ? ? ? ? ? ? 20 1 2 in aj figure 8. mode-recovery timing diagram sclk cs din d0?9 id/qd t/r rx - > tx adc digital output. sinad settles within 1db dac analog output. output settles to 10 lsb error 16-bit serial data input t enable , rx external t/r control t enable , tx external t/r control t wake, sd, st_ to tx mode or t enable , tx t wake, sd, st_ to rx mode or t enable , rx t/r tx - > rx
max19708 10-bit, 11msps, ultra-low-power analog front-end ______________________________________________________________________________________ 27 12-bit, auxiliary control dacs the max19708 includes three 12-bit aux-dacs (dac1, dac2, dac3) with 1? settling time for controlling vari- able-gain amplifier (vga), automatic gain-control (agc), and automatic frequency-control (afc) func- tions. the aux-dac output range is 0.1v to 2.56v. during power-up, the vga and agc outputs (dac2 and dac3) are at zero. the afc dac (dac1) is at 1.1v during power-up. the aux-dacs can be independently controlled through the spi bus, except during shdn mode where the aux-dacs are turned off completely and the output voltage is set to zero. in stby and idle modes the aux-dacs maintain the last value. on wakeup from shdn, the aux-dacs resume the last values. loading on the aux-dac outputs should be carefully observed to achieve specified settling time and stabili- ty. the capacitive load must be kept to a maximum of 5pf including package and trace capacitance. the resistive load must be greater than 200k . if capacitive loading exceeds 5pf, then add a 10k resistor in series with the output. adding the series resistor helps drive larger load capacitance (< 15pf) at the expense of slower settling time. 10-bit, 333ksps auxiliary adc the max19708 integrates a 333ksps, 10-bit aux-adc with an input 4:1 multiplexer. in the aux-adc mode reg- ister, setting bit ad0 begins a conversion with the auxil- iary adc. bit ad0 automatically clears when the conversion is complete. setting or clearing ad0 during a conversion has no effect (see table 12). bit ad1 determines the internal reference of the auxiliary adc (see table 13). bits ad2 and ad3 determine the auxil- iary adc input source (see table 14). bits ad4, ad5, and ad6 select the number of averages taken when a single start-convert command is given. the conversion time increases as the number of averages increases (see table 15). the conversion clock can be divided down from the system clock by properly setting bits ad7, ad8, and ad9 (see table 16). the aux-adc out- put data can be written out of dout by setting bit ad10 high (see table 17). the aux-adc features a 4:1 input multiplexer to allow measurements on four input sources. the input sources are selected by ad3 and ad2 (see table 14). two of the multiplexer inputs (adc1 and adc2) can be con- nected to external sources such as an rf power detec- tor like the max2208 or temperature sensor like the max6613. the other two multiplexer inputs are internal connections to v dd and ov dd that monitor the power- supply voltages. the internal v dd and ov dd connec- tions are made through integrated resistor-dividers that yield v dd / 2 and ov dd / 2 measurement results. the aux-adc voltage reference can be selected between an internal 2.048v bandgap reference or v dd (see table 13). the v dd reference selection is provided to allow measurement of an external voltage source with a full-scale range extending beyond the 2.048v level. the input source voltage range cannot extend above v dd . table 12. auxiliary adc convert table 13. auxiliary adc reference table 14. auxiliary adc input source ad0 selection 0 aux-adc idle (default) 1 aux-adc start-convert ad1 selection 0 internal 2.048v reference (default) 1 internal v dd reference ad3 ad2 aux-adc input source 0 0 adc1 (default) 0 1 adc2 10 v dd / 2 11 ov dd / 2
max19708 10-bit, 11msps, ultra-low-power analog front-end 28 ______________________________________________________________________________________ the conversion requires 12 clock edges (1 for input sampling, 1 for each of the 10 bits, and 1 at the end for loading into the serial output register) to complete one conversion cycle (when no averaging is being done). each conversion of an average (when averaging is set greater than 1) requires 12 clock edges. the conver- sion clock is generated from the system clock input (clk). an spi-programmable divider divides the sys- tem clock by the appropriate divisor (set with bits ad7, ad8, and ad9; see table 16) and provides the conver- sion clock to the auxiliary adc. the auxiliary adc has a maximum conversion rate of 333ksps. the maximum conversion clock frequency is 4mhz (333ksps x 12 clocks). choose the proper divider value to keep the conversion clock frequency under 4mhz, based upon the system clk frequency supplied to the max19708 (see table 16). the total conversion time (t conv ) of the auxiliary adc can be calculated as t conv = (12 x n avg x n div ) / f clk ; where n avg is the number of averages (see table 15), n div is the clk divisor (see table 16), and f clk is the system clk frequency. dout is normally in a tri-state condition. upon setting the auxiliary adc start conversion bit (bit ad0), dout becomes active and goes high, indicating that the aux- adc is busy. when the conversion cycle is complete (including averaging), the data is placed into an output register and dout goes low, indicating that the output data is ready to be driven onto dout. when bit ad10 is set (ad10 = 1), the aux-adc enters a data output mode where data is available on dout upon the next asser- tion low of cs . the auxiliary adc data is shifted out of dout (msb first) with the data transitioning on the falling edge of the serial clock (sclk). dout enters a tri-state condition when cs is deasserted high. when bit ad10 is cleared (ad10 = 0), the aux-adc data is not available on dout (see table 17). din can be written independent of dout state. a 16- bit instruction at din updates the device configuration. to prevent modifying internal registers while reading data from dout, hold din at a high state. this effec- tively writes all ones into address 1111. since address 1111 does not exist, no internal registers are affected. table 15. auxiliary adc averaging table 16. auxiliary adc clock (clk) divider table 17. auxiliary adc data output mode ad10 selection 0 aux-adc data is not available on dout (default) 1 aux-adc enters data output mode where data is available on dout ad6 ad5 ad4 aux-adc averaging 0 0 0 1 conversion (no averaging) (default) 0 0 1 average of 2 conversions 0 1 0 average of 4 conversions 0 1 1 average of 8 conversions 1 0 0 average of 16 conversions 1 0 1 average of 32 conversions 1 1 x average of 32 conversions ad9 ad8 ad7 aux-adc conversion clock 0 0 0 clk divided by 1 (default) 0 0 1 clk divided by 2 0 1 0 clk divided by 4 0 1 1 clk divided by 8 1 0 0 clk divided by 16 1 0 1 clk divided by 32 1 1 0 clk divided by 64 1 1 1 clk divided by 128 x = don? care.
max19708 10-bit, 11msps, ultra-low-power analog front-end ______________________________________________________________________________________ 29 reference configurations the max19708 features an internal precision 1.024v bandgap reference that is stable over the entire power- supply and temperature ranges. the refin input pro- vides two modes of reference operation. the voltage at refin (v refin ) sets the reference operation mode (table 18). in internal reference mode, connect refin to v dd . v ref is an internally generated 0.512v ?%. com, refp, and refn are low-impedance outputs with v com = v dd / 2, v refp = v dd / 2 + v ref / 2, and v refn = v dd / 2 - v ref / 2. bypass refp, refn, and com each with a 0.33? capacitor. bypass refin to gnd with a 0.1? capacitor. in buffered external reference mode, apply 1.024v ?0% at refin. in this mode, com, refp, and refn are low-impedance outputs with v com = v dd / 2, v refp = v dd / 2 + v refin / 4, and v refn = v dd / 2 - v refin / 4. bypass refp, refn, and com each with a 0.33? capacitor. bypass refin to gnd with a 0.1? capacitor. in this mode, the tx path full-scale output is proportional to the external reference. for example, if the v refin is increased by 10% (max), the tx path full- scale output is also increased by 10% or ?51mv. applications information using balun transformer ac-coupling an rf transformer (figure 9) provides an excellent solution to convert a single-ended signal source to a fully differential signal for optimum adc performance. connecting the center tap of the transformer to com provides a v dd / 2 dc level shift to the input. a 1:1 transformer can be used, or a step-up transformer can be selected to reduce the drive requirements. in gener- al, the max19708 provides better sfdr and thd with fully differential input signals than single-ended signals, especially for high input frequencies. in differential mode, even-order harmonics are lower as both inputs (iap, ian, qap, qan) are balanced, and each of the rx adc inputs only requires half the signal swing com- pared to single-ended mode. figure 10 shows an rf transformer converting the max19708 tx dac differen- tial analog outputs to single-ended. using op-amp coupling drive the max19708 rx adc with op amps when a balun transformer is not available. figures 11 and 12 show the rx adc being driven by op amps for ac-cou- pled single-ended and dc-coupled differential applica- tions. amplifiers such as the max4454 and max4354 provide high speed, high bandwidth, low noise, and table 18. reference modes v refin reference mode > 0.8v x v dd internal reference mode. v ref is internally generated to be 0.512v. bypass refp, refn, and com each with a 0.33? capacitor. 1.024v ?0% buffered external reference mode. an external 1.024v ?0% reference voltage is applied to refin. v ref is internally generated to be v refin / 2. bypass refp, refn, and com each with a 0.33? capacitor. bypass refin to gnd with a 0.1? capacitor. figure 9. balun transformer-coupled single-ended-to- differential input drive for rx adc com iap ian 25 0.1 f 0.33 f 25 0.1 f v in max19708 22pf 22pf qap qan 25 0.1 f 0.33 f 25 0.1 f v in 22pf 22pf
max19708 10-bit, 11msps, ultra-low-power analog front-end 30 ______________________________________________________________________________________ low distortion to maintain the input signal integrity. the op-amp circuit shown in figure 12 can also be used to interface with the tx dac differential analog outputs to provide gain or buffering. the tx dac differential ana- log outputs cannot be used in single-ended mode because of the internally generated common-mode level. also, the tx dac analog outputs are designed to drive a differential input stage with input impedance 70k . if single-ended outputs are desired, use an amplifier to provide differential-to-single-ended conver- sion and select an amplifier with proper input common- mode voltage range. tdd mode the max19708 is optimized to operate in td-scdma applications. when fast mode is selected, the max19708 can switch between tx and rx modes through the t/ r pin in typically 0.5?. the rx adc and tx dac operate independently. the rx adc and tx dac digital bus are shared forming a single 10-bit par- allel bus. using the 3-wire serial interface or external t/ r pin, select between rx mode to enable the rx adc or tx mode to enable the tx dac. when operating in rx mode, the tx dac bus is not enabled and in tx mode the rx adc bus is tri-stated, eliminating any unwanted spurious emissions and preventing bus con- tention. in tdd mode, the max19708 uses 41.1mw power in rx mode at f clk = 11mhz and the dac uses 42.3mw in tx mode. td-scdma application figure 13 illustrates a typical td-scdma application circuit. the max19708 is designed to interface directly with the max2507 and max2392 radio front-ends to provide a complete ?f-to-bits?front-end solution. the max19708 provides several features that allow direct interface to the max2392 and max2507: integrated tx filters reduce component count, lower cost, and meet td-scdma spectral mask requirements programmable dc common-mode tx output levels eliminate discrete dc-level-shifting components while preserving tx dac full dynamic range optimized tx full-scale output level eliminates dis- crete amplifiers for i/q gain control tx-i/q offset correction eliminates discrete trim dacs for offset trim to improve sideband/carrier suppression ? one microsecond settling time aux-dacs for vga and agc control allow fast, accurate tx power and rx gain control figure 10. balun transformer-coupled differential-to-single- ended output drive for tx dac max19708 idp idn v out qdp qdn v out figure 11. single-ended drive for rx adc max19708 0.1 f 1k 1k 100 100 c in 22pf c in 22pf qap qan com iap ian 0.1 f r iso 50 r iso 50 refp refn v in 0.1 f 1k 1k 100 100 c in 22pf c in 22pf 0.1 f r iso 50 r iso 50 refp refn v in
max19708 10-bit, 11msps, ultra-low-power analog front-end ______________________________________________________________________________________ 31 figure 13. typical application circuit for td-scdma radio dac3 rx-i rx encode max 19708 10-bit dac 10-bit adc 12-bit dac tx source half- duplex bus digital baseband asic t/r d9 d0 system control clk dist spi reg ref 1.024v buffer rx-q tx-i tx-q dac1 dac2 4:1 mux 10-bit, 333ksps v dd temperature measure 0v dd adc clk sclk din cs shdn dout refin refp refn com direct modulator pa detect vga tcxo filter zif receiver agc max2392 max2507 figure 12. rx adc dc-coupled differential drive max19708 iap com ian r iso 22 r iso 22 r11 600 r9 600 r3 600 r2 600 r1 600 r10 600 r8 600 r5 600 r4 600 r7 600 r6 600 c in 5pf c in 5pf
max19708 10-bit, 11msps, ultra-low-power analog front-end 32 ______________________________________________________________________________________ grounding, bypassing, and board layout the max19708 requires high-speed board layout design techniques. refer to the max19708 ev kit data sheet for a board layout reference. place all bypass capacitors as close to the device as possible, preferably on the same side of the board as the device, using surface-mount devices for minimum inductance. bypass v dd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? capacitor. bypass ov dd to ognd with a 0.1? ceramic capacitor in parallel with a 2.2? capacitor. bypass refp, refn, and com each to gnd with a 0.33? ceramic capacitor. bypass refin to gnd with a 0.1? capacitor. multilayer boards with separated ground and power planes yield the highest level of signal integrity. use a split ground plane arranged to match the physical loca- tion of the analog ground (gnd) and the digital output- driver ground (ognd) on the device package. connect the max19708 exposed backside paddle to gnd plane. join the two ground planes at a single point so the noisy digital ground currents do not inter- fere with the analog ground plane. the ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes. make this connection with a low-value, surface- mount resistor (1 to 5 ), a ferrite bead, or a direct short. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital system? ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from sensi- tive analog traces. make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. keep all signal lines short and free of 90 turns. dynamic parameter definitions adc and dac static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. the static lin- earity parameters for the device are measured using the best-straight-line fit (dac figure 14a). differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes (adc) and a monotonic transfer function (adc and dac) (dac figure 14b). adc offset error ideally, the midscale transition occurs at 0.5 lsb above midscale. the offset error is the amount of deviation between the measured transition point and the ideal transition point. dac offset error offset error (figure 14a) is the difference between the ideal and actual offset point. the offset point is the out- put value when the digital input is midscale. this error affects all codes by the same amount and usually can be compensated by trimming. 0 2 1 4 3 7 6 5 000 010 001 011 100 101 110 at step 011 (0.5 lsb) at step 001 (0.25 lsb) 111 digital input code analog output value figure 14a. integral nonlinearity 0 2 1 4 3 6 5 000 010 001 011 100 101 differential linearity error (-0.25 lsb) differential linearity error (+0.25 lsb) 1 lsb 1 lsb digital input code analog output value figure 14b. differential nonlinearity
max19708 10-bit, 11msps, ultra-low-power analog front-end ______________________________________________________________________________________ 33 adc gain error ideally, the adc full-scale transition occurs at 1.5 lsb below full scale. the gain error is the amount of devia- tion between the measured transition point and the ideal transition point with the offset error removed. adc dynamic parameter definitions aperture jitter figure 15 shows the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 15). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error) and results directly from the adc? resolution (n bits): snr(max) = 6.02db x n + 1.76db (in db) in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spec- tral components to the nyquist frequency excluding the fundamental, the first five harmonics, and the dc offset. signal-to-noise and distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise. rms noise includes all spectral components to the nyquist frequency excluding the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: enob = (sinad - 1.76) / 6.02 total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude and v 2 ? 6 are the amplitudes of the 2nd- through 6th-order harmonics. third harmonic distortion (hd3) hd3 is defined as the ratio of the rms value of the third harmonic component to the fundamental input signal. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest spurious component, excluding dc offset. intermodulation distortion (imd) imd is the total power of the intermodulation products relative to the total input power when two tones, f 1 and f 2 , are present at the inputs. the intermodulation products are (f 1 ? 2 ), (2 ? f 1 ), (2 ? f 2 ), (2 ? f 1 ? 2 ), (2 ? f 2 ? 1 ). the individual input tone levels are at -7dbfs. 3rd-order intermodulation (im3) im3 is the power of the worst 3rd-order intermodulation product relative to the input power of either input tone when two tones, f 1 and f 2 , are present at the inputs. the 3rd-order intermodulation products are (2 x f 1 ? 2 ), (2 ? f 2 ? 1 ). the individual input tone levels are at -7dbfs. power-supply rejection power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ?%. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc in such a way that the signal? slew rate does not thd (v +v +v +v +v ) v 2 2 3 2 4 2 5 2 6 2 1 = ? ? ? ? ? ? ? ? 20 x log hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 15. t/h aperture timing
max19708 10-bit, 11msps, ultra-low-power analog front-end 34 ______________________________________________________________________________________ limit the adc? performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. note that the t/h performance is usually the limiting factor for the small-signal input bandwidth. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. this point is defined as the full- power bandwidth frequency. dac dynamic parameter definitions total harmonic distortion thd is the ratio of the rms sum of the output harmonics up to the nyquist frequency divided by the fundamental: where v 1 is the fundamental amplitude and v 2 through v n are the amplitudes of the 2nd through nth harmonic up to the nyquist frequency. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest distortion component up to the nyquist frequency excluding dc. thd (v + v + ... + v ) v 2 2 3 2 n 2 1 = ? ? ? ? ? ? ? ? 20 x log selector guide part description sampling rate (msps) max19700 dual 10-bit rx adc, dual 10-bit tx dac, integrated td-scdma filters, three 12-bit auxiliary dacs 7.5 max19708 dual 10-bit rx adc, dual 10-bit tx dac, integrated td-scdma filters, three 12-bit auxiliary dacs, 10-bit auxiliary adc with 4:1 input mux 11 max19705/max19706 ? /max19707 ? dual 10-bit rx adc, dual 10-bit tx dac, three 12-bit auxiliary dacs, 10-bit auxiliary adc with 4:1 input mux 7.5/22/45 ? future product?ontact factory for availability.
max19708 10-bit, 11msps, ultra-low-power analog front-end ______________________________________________________________________________________ 35 clk serial interface and system control iap ian qap qan idp idn qdp qdn refp refn com dout refin din sclk cs system clock programmable offset/gain/cm 1.024v reference buffer 10-bit adc 10-bit adc 10-bit dac half- duplex bus 10-bit dac 12-bit dac 12-bit dac 12-bit dac 4:1 mux gnd v dd 0v dd dac1 dac2 dac3 adc1 d0?9 shdn t/r max19708 10-bit adc adc2 ognd v dd = +2.7v to +3.3v ov dd = +1.8v to +3.3v filter filter functional diagram
max19708 10-bit, 11msps, ultra-low-power analog front-end 36 ______________________________________________________________________________________ 32, 44, 48l qfn .eps e l e l a1 a a2 e/2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k detail b e l l1 proprietary information document control no. approval title: rev. 2 1 21-0144 dallas semiconductor package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm d package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max19708 10-bit, 11msps, ultra-low-power analog front-end maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 37 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. proprietary information document control no. approval title: rev. 2 2 21-0144 dallas semiconductor package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm d package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) springer
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max19708 part number table notes: see the max19708 quickview data sheet for further information on this product family or download the max19708 full data sheet (pdf, 560kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max19708evc modu -40c to +85c rohs/lead-free: no max19708evc mod2 -40c to +85c rohs/lead-free: no max19708etm thin qfn;48 pin;7x7x0.8mm dwg: 21-0144f (pdf) use pkgcode/variation: t4877-4 * -40c to +85c rohs/lead-free: no materials analysis max19708etm+ thin qfn;48 pin;7x7x0.8mm dwg: 21-0144f (pdf) use pkgcode/variation: t4877+4 * -40c to +85c rohs/lead-free: yes materials analysis max19708etm+t thin qfn;48 pin;7x7x0.8mm dwg: 21-0144f (pdf) use pkgcode/variation: t4877+4 * -40c to +85c rohs/lead-free: yes materials analysis MAX19708ETM-T -40c to +85c rohs/lead-free: no didn't find what you need?
c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

▲Up To Search▲

Price & Availability of MAX19708ETM-T

	To Download MAX19708ETM-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .